Part Number Hot Search : 
ZQB50L AD7701 2412DH MAX27 62351 CMHZ4616 MSK4362U 30PHA2
Product Description
Full Text Search
 

To Download LIS2L02AS4 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 LIS2L02AS4
INERTIAL SENSOR: 2Axis - 2g/6g LINEAR ACCELEROMETER
PRODUCT PREVIEW


2.4V TO 5.25V SINGLE SUPPLY OPERATION THE SENSITIVITY IS ADJUSTED WITH A TOTAL ACCURACY OF 10% THE OUTPUT VOLTAGE, OFFSET, SENSITIVITY AND TEST VOLTAGE ARE RATIOMETRIC TO THE SUPPLY VOLTAGE DEVICE SENSITIVITY IS ON-CHIP FACTORY TRIMMED EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY
SO-24 ORDERING NUMBER: LIS2L02AS4
DESCRIPTION The LIS2L02AS4 is a dual-axis linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide an analog signal to the external world. The sensing element, capable to detect the acceleration, is manufactured using a dedicated process called THELMA (Thick Epi-Poly Layer for Microactuators and Accelerometers) developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS2L02AS4 has a user selectable full scale of 2g, 6g and it is capable of measuring accelerations BLOCK DIAGRAM
over a maximum bandwidth of 4.0 KHz for both the X and Y axis. The device bandwidth may be reduced by using external capacitances. A self-test capability allows the user to check the functioning of the system. The LIS2L02AS4 is available in plastic SMD package and it is specified over a temperature range extending from -40C to +85C. The LIS2L02AS4 belongs to a family of products suitable for a variety of applications: - Antitheft systems - Inertial navigation - Virtual reality input devices - Vibration Monitoring, recording and compensation - Appliance control - Robotics
Routx S1X S1Y CHARGE AMPLIFIER S/H
Voutx
rot
S2Y S2X
MUX
DEMUX
Routy S/H
Vouty
VOLTAGE & CURRENT REFERENCE
TRIMMING CIRCUIT & TEST INTERFACE
CLOCK & PHASE GENERATOR
February 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/7
LIS2L02AS4
PIN DESCRIPTION
N 1 to 5 6 7 8 9 10 11 12 13 14-15 16 17 18 19 to 24 Pin NC GND Vdd Vouty ST Voutx PD NC FS Reserved Reserved Reserved Reserved NC Internally not connected 0V supply Power supply Output Voltage Self Test (Logic 0: normal mode; Logic 1: Self-test) Output Voltage Power Down (Logic 0: normal mode; Logic 1: Power-Down mode) Internally not connected Full Scale selection (Logic 0: 2g Full-scale; Logic 1: 6g Full-scale) Leave unconnected or connect to Vdd Connect to Vdd or ground Leave unconnected or connect to Vdd Leave unconnected or connect to ground Internally not connected Function
PIN CONNECTION (Top view)
NC NC
1 Y
NC NC NC NC NC
NC reserved reserved reserved reserved reserved FS
NC NC NC
13 X
GND Vdd Vouty ST Voutx PD NC
DIRECTION OF THE DETECTABLE ACCELERATIONS
2/7
LIS2L02AS4
ELECTRICAL CHARACTERISTCS (Temperature range -40C to +85C) All the parameters are specified @ Vdd=3.3V and T=25C unless otherwise noted
Symbol Vdd Idd Voff Ar Parameter Supply voltage Supply current Zero-g level Acceleration range2 T = 25C ratiometric to Vdd 0V on FS pin Vdd on FS pin So Sensitivity ratiometric to Vdd T = 25C Full-scale = 2g T = 25C Full-scale = 6g NL Non Linearity Best fit straight line X, Y axis Full-scale = 2g X, Y axis Vdd=5V Full-scale = 2g T = 25C Vdd=3.3V T = 25C Vdd=5V Vst Self test input Logic 0 level Logic 1 level Rout Cload Output impedance Capacitive load drive3 320 0 2.8 100 Vdd/5-10% Vdd/15-10% Vdd/2-18% 1.8 Test Condition Min. 2.4 850 Vdd/2 2.0 6.0 Vdd/5 Vdd/15 1 Vdd/5+10% Vdd/15+10% Vdd/2+18% 2.2 Typ.1 Max. 5.25 Unit V A V g g V/g V/g % FS
fuc an Vt
Sensing Element Resonant Frequency Acceleration noise density Self test output voltage Ratiometric to Vdd
4.0 50 27 95 0.8 Vdd
KHz g/ Hz mV mV V V
k
pF
Notes: 1. Typical specifications are not guaranteed 2. Guaranteed by wafer level test and measurement of initial offset and sensitivity 3. Bandwidth=1/(2**100K*Cload)
3/7
LIS2L02AS4
ABSOLUTE MAXIMUM RATING Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol Vdd Vin APOW AUNP TOP TSTG Supply voltage Input voltage on any control pin (FS, PD, ST) Acceleration (Any axis, Powered, Vdd=3.3V) Acceleration (Any axis, Unpowered) Operating Temperature Range Storage Temperature Range Ratings Maximum Value -0.3 to 6 Vss -0.3 to Vdd +0.3 3000g for 0.5 ms 3000g for 0.5 ms -40 to +85 -40 to +105 C C Unit V V
1
FUNCTIONALITY
The LIS2L02AS4 is a low-cost, analog output two-axis linear accelerometer packaged in SO24 package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide an analog signal to the external world.
1.1 Sensing element The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase. The equivalent circuit for the sensing element is shown in the below figure; when a linear acceleration is applied, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum variation of the capacitive load is few tenth of pF.
4/7
LIS2L02AS4
Figure 1. Equivalent electrical circuit
Cps1
Rs1 S1x Cs1x
Cpr
Rr
Cs2x S2x Cps2 Cps1 Rs2 Rs1 S1y Cs1y rot
Cpr
Rr
Cs2y S2y Cps2 Rs2
The complete signal processing uses a fully differential structure, while the final stage converts the differential signal into a single-ended one to be compatible with the external world. The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its output to cancel the offset and the 1/f noise. The produced signal is then sent to two different S&Hs, one for each channel, and made available to the outside. The low noise input amplifier operates at 200 kHz while the two S&Hs operate at a sampling frequency of 66 kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output waveform. All the analog parameters (output offset voltage and sensitivity) are ratiometric to the voltage supply: increasing or decreasing the voltage supply, the sensitivity and the offset will increase or decrease accordingly. This feature provides the cancellation of the error related to the voltage supply along an analog to digital conversion chain.
1.2 Factory calibration The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters which are trimmed are: gain, offset, common mode and internal clock frequency. The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation thus allowing the final user to employ the device without any need for further calibration
5/7
LIS2L02AS4
DIM. MIN. A A1 A2 B C D E e H h k L 0.40 10.0 0.25 0.33 0.23 15.20 7.40 2.35 0.10
mm TYP. MAX. 2.65 0.30 2.55 0.51 0.32 15.60 7.60 1.27 10.65 0.75 0.394 0.010 0.013 0.009 0.598 0.291 MIN. 0.093 0.004
inch TYP. MAX. 0.104 0.012 0.100 0.0200 0.013 0.614 0.299 0,050 0.419 0.030
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.)
SO24
1.27 0.016 0.050
h x 45
A2
A1
A
0.10mm .004 Seating Plane
B
e
K L H
A1
C
D
24
13
1
12
SO24
6/7
E
LIS2L02AS4
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
7/7


▲Up To Search▲   

 
Price & Availability of LIS2L02AS4

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X